Summary: Resonac has successfully produced a 300mm silicon carbide (SiC) single crystal and substrate, marking a major step toward lower-cost, high-volume SiC semiconductor manufacturing.

 

---

Japanese materials manufacturer Resonac announced on September 15, 2026, that it has successfully grown a 300mm (12-inch) silicon carbide (SiC) single crystal and processed it into a substrate, reaching one of the largest SiC wafer sizes currently under development worldwide.

 

 

The breakthrough represents a significant milestone for the silicon carbide wafer, SiC substrate, and power semiconductor industries, which are rapidly expanding to support electric vehicles, AI data centers, renewable energy systems, and next-generation power electronics. Resonac currently supplies 150mm SiC epitaxial wafers and has already begun shipping 200mm products. The 300mm development was supported by Japan’s NEDO Green Innovation Fund program.

 

Resonac joins a growing list of companies pursuing 12-inch SiC technology. China's SICC (TankeBlue) unveiled a 300mm conductive SiC substrate in late 2024, while U.S.-based Wolfspeed announced a 300mm SiC crystal wafer platform earlier this year targeting AI data center power delivery and future XR applications. In August, Coherent disclosed shipments of sample 300mm high-thermal-conductivity SiC substrates designed to improve semiconductor cooling performance.

 

 

The industry’s push toward larger wafers is driven primarily by manufacturing economics. Silicon carbide substrates account for nearly half of the total cost of SiC devices. A 300mm wafer provides approximately 2.25 times the surface area of a 200mm wafer, potentially increasing the number of usable chips per wafer by around 2.5 times. Industry estimates suggest that large-scale production of 300mm SiC substrates could reduce per-wafer costs by as much as 40%.

 

As demand for high-efficiency power devices continues to grow, the transition to larger-diameter SiC wafers is expected to play a key role in scaling production and lowering costs across the semiconductor supply chain.